Printed circuits are used in a wide variety of electronic equipment and utilize graphic technologies to achieve a great advantage in the size, weight, and cost of equipment compared to conventional wiring arrangements. Typically, an enlarged-scale artwork master of a circuit pattern of circuit elements and conductor paths is first prepared, and then the enlarged-scale artwork master is photographically reduced to the desired size. Screens and masks are fabricated according to the reduced master of the circuit pattern for the application of photoresistive materials to circuit board layers. Processes including etching, screening, plating, laminating, vacuum deposition, diffusion, and application of protective coatings are used to provide printed circuits.
Multilayer printed wiring boards are often used in applications requiring increased circuit density, and facilitate the provision of additional leads to an electrical component. Conductors are located on several insulated internal layers. Common multilayer circuits include a number of two-sided etched copper foil boards, separated by an insulating layer and laminated together under controlled temperature, pressure, and time.
Several techniques are known for electrically interconnecting the conductors on multiple layers of the multilayer printed wiring boards. According to one technique, a hole or "via" is drilled through the multilayer board from one side to the other. The drilled cylindrical surface is plated by a chemical deposition process and then electroplated to form the interconnections between layers or mountings for electronic parts.
U.S. Pat. No. 4,980,034 provides a general overview of other conventional methods, e.g., subtractive, semi-additive, and additive methods, used in fabricating multilayer interconnects and further discloses a "modified semi-additive" process. In the process disclosed in U.S. Pat. No. 4,980,034, a chromium protective layer is deposited on a silicon substrate and is patterned. A continuous copper layer is deposited over the patterned chromium layer, and a protective chromium overcoat covers the copper layer. A dielectric is applied over the overcoat; openings extending to the copper layer are etched in the dielectric and the overcoat; and via posts are plated in the openings using the copper layer as a cathode. Second bottom protective layers, conductive layers, and top protective layers are deposited over the dielectric and patterned, and the process of applying a dielectric, etching openings, plating via holes using the immediately preceding conductive layer as a cathode, and depositing and patterning further protective and conductive layers is repeated until a desired number of patterned conductive layers are provided. The substrate is removed, e.g., by etching, and the initial conductive layer and the overcoat is etched, the patterned protective layer preventing etching of the unexposed areas of the conductive layer, thereby creating a flex circuit. The flex circuit may then be bonded to another substrate.
Conventional methods for forming interconnects have various drawbacks. Techniques involving drilling holes for vias are, of course, subject to mechanical limitations. As discussed in U.S. Pat. No. 4,980,034, subtractive techniques result in vias having sloped sides, requiring more area; the vias may have to be laterally offset, requiring more area, reducing heat transfer, and extending the conductive path; and design rules become complex. Semi-additive processes involve many steps and require a planarization process to expose vias and, in additive processes, it is difficult to control via uniformity. In the process described in U.S. Pat. No. 4,980,034, laser etching of the vias through the dielectric must be performed one via at a time, resulting in a time-consuming process. Further, vapor deposition process steps are costly, and it is necessary to discard the substrate prior to etching the bottom circuit pattern.
It is, accordingly, desirable to provide a method that permits efficiently forming uniform, straight sided, vertically stacked vias in a multilayer printed wiring board, without the need for vapor deposition or mechanical processing such as drilling or planarization. It is further desirable to provide a system for performing the method.
In accordance with one aspect of the present invention, a method of fabricating a multilayer laminate for a printed wiring board is disclosed. According to the method, a photoimage of a plurality of blind via sites is developed, with photoimaging material, on a first side of a first sheet, the first sheet including a flexible dielectric material, the flexible material being clad on the first and a second side with first and second layers of conductive material, respectively. Conductive material of the first layer of conductive material is etched from the blind via sites. Developed photoimaging material of the photoimage of the blind via sites is removed. The flexible material is laser ablated from the blind via sites. A photoimage of a conductor and pad pattern is developed, with photoimaging material, on the first side of the first sheet. Conductive material posts are electroplated in the blind via sites, using the second layer of conductive material as an electrode. Conductive material is electroplated in the conductor and pad pattern on the first side of the first sheet. A protective material is electroplated in the conductor and pad pattern over the conductive material electroplated in the conductor and pad pattern on the first side of the first sheet. Developed photoimaging material of the photoimage of the conductor and pad pattern is removed. The first side of the first sheet is etched to remove the photoimaged pattern and exposed conductive material of the first layer of conductive material beneath the photoimaged pattern, thereby forming a patterned first sheet. The protective material is removed. Steps of bonding a first side of a second sheet, the second sheet including a flexible material clad on a second side with a first layer of conductive material, to an etched first side of a preceding sheet, followed by a patterning operation for each additional layer of conductive material desired, are repeated, thereby forming the multilayer laminate.
In accordance with another aspect of the present invention, a method of fabricating a multilayer laminate for a printed wiring board is disclosed. According to the method, a plurality of blind via sites is etched from a first side of a first sheet, the first sheet including a flexible dielectric material, the flexible material being clad on the first and a second side with first and second layers of conductive material, respectively, through the first conductive material and the flexible material to the second conductive material. Conductive material posts are electroplated in the blind via sites, using the second layer of conductive material as an electrode.
In accordance with another aspect of the present invention, a system for fabricating a multilayer laminate for a printed wiring board is disclosed. The system includes means for forming a photoimage of a plurality of blind via sites on a first side of a first sheet, the first sheet including a flexible dielectric material, the flexible material being clad on the first and a second side with first and second layers of conductive material, respectively. Means are also provided for etching conductive material from the blind via sites. A laser is provided for ablating the flexible material from the blind via sites. Means are provided for forming a photoimage of a conductor and pad pattern on the first side of the first sheet after laser etching. Means are provided for electroplating conductive material posts in the blind via sites after laser etching, using the second layer of conductive material as an electrode, and for electroplating conductive material in the conductor and pad pattern on the first side of the first sheet after electroplating the conductive material posts. Means are provided for electroplating a protective material in the conductor and pad pattern over the conductive material electroplated in the conductor and pad pattern on the first side of the first sheet. Means are also provided for etching the first side of the first sheet to remove the photoimaged pattern and exposed conductive material of the first layer of conductive material beneath the photoimaged pattern, thereby forming a patterned first sheet.
In accordance with another aspect of the present invention, a system for fabricating a multilayer laminate for a printed wiring board is disclosed. The system includes means for forming a photoimage of a plurality of blind via sites on a first side of a first sheet, the first sheet including a flexible dielectric material, the flexible material being clad on the first and a second side with first and second layers of conductive material, respectively. Means are provided for etching conductive material from the blind via sites. Means are provided for laser ablating the flexible material from the blind via sites. Means are also provided for electroplating conductive material posts in the blind via sites after laser ablating, using the second layer of conductive material as an electrode.
In accordance with yet another aspect of the present invention, a multilayer laminate for a printed wiring board is disclosed. The multilayer laminate includes a first sheet, the first sheet including a flexible dielectric material, the flexible material being clad on a first and a second side with first and second layers of conductive material, respectively. The multilayer laminate further includes blind via sites extending through the first layer of conductive material and the flexible material to the second layer of conductive material, and conductive material posts electroplated in the blind via sites by using the second layer of conductive material as an electrode.